ARM, the leading chipmaker for mobile device microprocessors, is getting greener in its new chip design scheme. ARM is claiming 70 percent processor power savings with a new chip design called Big.Little, and mobile devices on display at the Mobile World Congress in Barcelona, Spain over the last couple days offered an initial glimpse of this electronic green technology. The Mobile World Congress is the one of the primary events annually for showcasing advanced technology for mobile devices.
The Big.Little chip power-savings is based on the diversion of lower performance functions such as voicemails, messaging, MP3 and other basic tasks to low-power cores of the chip, directing the high-performance cores to focus on more complex, power-sensitive activities. The technology offers an upgrade in energy-efficiency to today’s ARM processor designs, which do not effectively differentiate tasks between low- and high-performance CPUs, leading to higher power consumption and the need for daily battery charging of smartphones and other mobile devices.
The benefits of the ARM Big.Little chip design were highlighted in a quad-core smartphone shown by chipmaker Renesas and a prototype tablet with a Samsung eight-core chip shown in ARM’s booth at the Mobile World Congress. The Big.Little concept couples high-performance with low-power cores in one chip, with tasks being assigned to specific cores based on their power requirements and priority, as more electronics seek greener horizons via power-savings benefits.
Big.Little has already been licensed by seven chipmakers including Renesas and Samsung, and a glimpse of the technology was provided in devices containing chips from those companies at the Congress in Barcelona. A quad-core chip is the emerging option for smartphones, which are more sensitive to power requirements than other mobile devices. Along those same lines, new semiconductor technology is being developed at a more fundamental level, down to the transistor structure, to facilitate the power-savings of future computers and mobile devices. New smartphones incorporating this more energy-efficient chip design are projected to be shipped by the end of 2013.
A fully-depleted (FD) transistor design is being considered for next-generation electronic device technology, which is compatible with 2D or emerging 3D designs. It is in direct contrast with other technologies applied today. The current between source and drain is allowed to flow only through a thin silicon region, defined by the physical parameters of the transistor.
In the planar version of fully-depleted technology, transistors are built flat on a silicon wafer. In the three-dimensional design, a thin vertical “fin” of silicon with larger surface area is fabricated in which current will flow from the source to the drain of the device. In addition, FD transistors can reduce or possibly eliminate the need for implanting electrically-active dopant atoms into the channel for increased mobility and response time. These improvements help chipmakers obtain gains in both power-savings and performance that are essential in scaling silicon chip technology.
For planar or 2D device architecture, fully-depleted silicon-on-insulator (FD-SOI) schemes are currently being explored at the 28-nm chip node by major semiconductor companies such as ST Microelectronics and its partner ST-Ericsson. FD-SOI devices differ from conventional silicon-built devices in that the silicon junction is formed above an electrical insulator such as silicon dioxide. Allowing for a smooth evolution from conventional planar transistor technology, FD-SOI is a comparatively simple technology, with its proponents stating that both power consumption and performance metrics are comparable to those of FinFETs and lessening the need for aggressive shrinks in chip geometry every couple years.
The FinFET is competitive 3D chip technology, being pursued by industry-leading chipmakers such as Intel, Samsung and TSMC, whom are ramping up their pursuits of ARM in this space, that is more complex but has limitations for shrinking chip nodes sizes amid the lack of sufficient direct patterning techniques for next-generation devices.
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